abstract={In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a critical role in achieving high performance in many modern pipelined microprocessor architectures. Two-way branching is usually implemented with a conditional jump instruction. A conditional jump can either be "taken" and jump to a different place in program memory, or it can be "not taken" and continue execution immediately after the conditional jump. It is not known for certain whether a conditional jump will be taken or not taken until the condition has been calculated and the conditional jump has passed the execution stage in the instruction pipeline (see fig. 1). Without branch prediction, the processor would have to wait until the conditional jump instruction has passed the execute stage before the next instruction can enter the fetch stage in the pipeline. The branch predictor attempts to avoid this waste of time by trying to guess whether the conditional jump is most likely to be taken or not taken. The branch that is guessed to be the most likely is then fetched and speculatively executed. If it is later detected that the guess was wrong, then the speculatively executed or partially executed instructions are discarded and the pipeline starts over with the correct branch, incurring a delay. The time that is wasted in case of a branch misprediction is equal to the number of stages in the pipeline from the fetch stage to the execute stage. Modern microprocessors tend to have quite long pipelines so that the misprediction delay is between 10 and 20 clock cycles. As a result, making a pipeline longer increases the need for a more advanced branch predictor.The first time a conditional jump instruction is encountered, there is not much information to base a prediction on. But the branch predictor keeps records of whether branches are taken or not taken. When it encounters a conditional jump that has been seen several times before, then it can base the prediction on the history. The branch predictor may, for example, recognize that the conditional jump is taken more often than not, or that it is taken every second time. Branch prediction is not the same as branch target prediction. Branch prediction attempts to guess whether a conditional jump will be taken or not. Branch target prediction attempts to guess the target of a taken conditional or unconditional jump before it is computed by decoding and executing the instruction itself. Branch prediction and branch target prediction are often combined into the same circuitry.},
abstract={In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a critical role in achieving high performance in many modern pipelined microprocessor architectures. Two-way branching is usually implemented with a conditional jump instruction. A conditional jump can either be "taken" and jump to a different place in program memory, or it can be "not taken" and continue execution immediately after the conditional jump. It is not known for certain whether a conditional jump will be taken or not taken until the condition has been calculated and the conditional jump has passed the execution stage in the instruction pipeline (see fig. 1). Without branch prediction, the processor would have to wait until the conditional jump instruction has passed the execute stage before the next instruction can enter the fetch stage in the pipeline. The branch predictor attempts to avoid this waste of time by trying to guess whether the conditional jump is most likely to be taken or not taken. The branch that is guessed to be the most likely is then fetched and speculatively executed. If it is later detected that the guess was wrong, then the speculatively executed or partially executed instructions are discarded and the pipeline starts over with the correct branch, incurring a delay. The time that is wasted in case of a branch misprediction is equal to the number of stages in the pipeline from the fetch stage to the execute stage. Modern microprocessors tend to have quite long pipelines so that the misprediction delay is between 10 and 20 clock cycles. As a result, making a pipeline longer increases the need for a more advanced branch predictor.The first time a conditional jump instruction is encountered, there is not much information to base a prediction on. But the branch predictor keeps records of whether branches are taken or not taken. When it encounters a conditional jump that has been seen several times before, then it can base the prediction on the history. The branch predictor may, for example, recognize that the conditional jump is taken more often than not, or that it is taken every second time. Branch prediction is not the same as branch target prediction. Branch prediction attempts to guess whether a conditional jump will be taken or not. Branch target prediction attempts to guess the target of a taken conditional or unconditional jump before it is computed by decoding and executing the instruction itself. Branch prediction and branch target prediction are often combined into the same circuitry.},
file={/home/maths-lap-246/snap/zotero-snap/common/Zotero/storage/YSGI3IVN/Bridgeland - 2008 - Stability conditions on K3 surfaces.pdf}
}
@article{BridgelandTom2007SCoT,
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@@ -69,7 +67,7 @@
}
@article{JardimMarcos2019Waaf,
title={Walls and Asymptotics for {{Bridgeland}} Stability Conditions on 3-Folds},
title={Walls and Asymptotics for {{Bridgeland}} Stability Conditions on 3-{{Folds}}},
author={Jardim, Marcos and Maciocia, Antony},
date={2019},
abstract={Épijournal de Géométrie Algébrique, Volume 6 (2022), Article No. 22 We consider Bridgeland stability conditions for three-folds conjectured by Bayer-Macrì-Toda in the case of Picard rank one. We study the differential geometry of numerical walls, characterizing when they are bounded, discussing possible intersections, and showing that they are essentially regular. Next, we prove that walls within a certain region of the upper half plane that parametrizes geometric stability conditions must always intersect the curve given by the vanishing of the slope function and, for a fixed value of s, have a maximum turning point there. We then use all of these facts to prove that Gieseker semistability is equivalent to asymptotic semistability along a class of paths in the upper half plane, and to show how to find large families of walls. We illustrate how to compute all of the walls and describe the Bridgeland moduli spaces for the Chern character (2,0,-1,0) on complex projective 3-space in a suitable region of the upper half plane.},
abstract={In this paper, we shall study the structure of walls for Bridgeland’s stability conditions on abelian surfaces. In particular, we shall study the structure of walls for the moduli spaces of rank 1 complexes on an abelian surface with the Picard number 1.},
copyright={Springer-Verlag Berlin Heidelberg 2013},
langid={english},
keywords={Mathematics,Mathematics and Statistics,Physical Sciences,Science & Technology},
file={/home/maths-lap-246/snap/zotero-snap/common/Zotero/storage/8ZXVDQTC/Yanagida and Yoshioka - 2014 - Bridgeland’s stabilities on abelian surfaces.pdf}
